Improving the Fidelity of CNOT Circuits on NISQ Hardware

We introduce an improved CNOT synthesis algorithm that accounts for nearest-neighbour interactions and CNOT gate error rates in noisy intermediate-scale quantum (NISQ) hardware. Our contribution is twofold. First, we define a cost function, $Cost$, by approximating the average gate fidelity $F_{avg}$. According to the simulation results, $Cost$ fits the error probability of a noisy CNOT circuit, $Prob = 1 - F_{avg}$, much tighter than the commonly used cost functions. On IBM's fake Nairobi backend, it fits $Prob$ with an error at most $10^{-3}$. On other backends, it fits $Prob$ with an error at most $10^{-1}$. Moreover, it circumvents the computation complexity of calculating $F_{avg}$ and shows remarkable scalability.

Second, we propose an architecture-aware CNOT synthesis algorithm, NAPermRowCol, by adapting the leading Steiner-tree-based synthesis algorithms. A weighted edge is used to encode a CNOT gate error rate and $Cost$-instructed heuristics are applied to each reduction step. NAPermRowCol is benchmarked against the state-of-the-art CNOT synthesis algorithms in terms of the $Cost$ metric and the synthesized CNOT count. On average, for all input CNOT circuits with no more than 16 qubits, it is 2 times cheaper than Qiskit and it reduces the synthesized gate count by 20 times. Compared with algorithms that are noise-agnostic, it is effective and scalable to improve the fidelity of CNOT circuits. Depending on the benchmark circuit and the IBM backend selected, it lowers the synthesized CNOT count up to $58.71%$ compared to ROWCOL and up to $17.25%$ compared to PermRowCol. Moreover, it reduces the $Cost$ of a synthesized CNOT circuit, up to $56.92%$ compared to ROWCOL and up to $21.6%$ compared to PermRowCol.

Joint-work with: Dohun Kim, Minyoung Kim, and Michele Mosca

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